1. Field of the Invention
The present invention relates to a resistance change memory. In particular, it relates to a defect remedy technology of a resistance change memory.
2. Description of the Related Art
In recent years, with the popularization of cellular phones and portable audio players, semiconductor memories have been mounted in such electronic devices.
In the semiconductor memory, a redundant cell array of an arbitrary scale is provided in the same chip as that of a memory cell array to remedy a defective cell in the memory cell array. For the semiconductor memory, there is employed a technique for remedying the defect of memory cells by using redundant cells in this redundant cell array instead of the accidentally generated defective cell (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2003-272397).
A defective cell remedy method usually remedies the defective cell every unit of a word line including the defective cell or a bit line including the defective cell with respect to a plurality of two-dimensionally arranged memory cells.
In the remedy method of the word line unit (hereinafter referred to as the row remedy method), a row address including the defective cell (hereinafter referred to as the defect address) is beforehand stored in a memory chip by use of fuses or the like. Then, when a row address input from the outside matches the stored defect address, the word line including the defective cell is deactivated, and the word line connected to the redundant cell (hereinafter referred to as the redundant word line) is activated to remedy the defective cell.
Meanwhile, in a volatile semiconductor memory such as a dynamic random access memory (DRAM), a refresh operation is necessary. Further, in the DRAM, the cycle number of the refresh operation is regulated by a memory capacity, and hence there is a restriction that the number of the memory cells as the targets of the refresh operation is determined in one cycle. Therefore, in the DRAM, it is impossible to partially activate one word line in the memory cell array owing to the specifications of the operation of the word line.
That is, in the DRAM, the matching state of the specifications of the refresh cycle with the operation has to be secured. Therefore, even if the number of the defective cell included in one word line is one, this word line is replaced with one redundant word line. In consequence, to remedy two defective cells included in different row addresses (word lines) of the memory cell array, two redundant word lines are necessary.
Thus, when the row remedy method is used for the DRAM, the redundant word lines as many as the word lines connected to the defective cells are necessary, regardless of the number of the defective cells connected to one word line.
In this case, when the number of the defective cells increases with the increase of the memory capacity and the miniaturization of the memory cells, and the number of the redundant word lines (the redundant cells) to be mounted also increase. That is, the defective cells increase with the capacity enlargement and the size miniaturization of the memory, but in such a case, the improvement of the remedy efficiency of the defective cells may cause the increase of a chip area and the increase of a manufacturing cost.
The semiconductor memory expected as a substitute for the DRAM, for example, no magnetoresistive random access memory (MRAM) require a refresh operation, and hence the above restriction on the refresh operation can be eliminated, and therefore there is desired the realization of the row remedy method having a higher remedy efficiency.